1. Field of the Invention
The present invention generally relates to the design and testing of semiconductor chips and integrated circuits, and more particularly to a method of simulating circuit operation using netlists and transient analysis.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A digital microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements grouped to perform a logic function. Cell types include, for example, core cells, scan cells, memory cells and input/output (I/O) cells.
An IC chip is fabricated by first conceiving the logical circuit description, and then converting that logical description into a physical description, or geometric layout. The physical design process is usually carried out using a “netlist,” which is a record of all of the nets, or interconnections, between the cell pins. A layout typically consists of a set of planar geometric shapes in several layers. The layout is then checked to ensure that it meets all of the design requirements, particularly timing requirements. The result is a set of design files known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator. During fabrication, these masks are used to pattern one or more dies on a silicon wafer using a sequence of photolithographic steps.
Due to the large number of components and the details required by the fabrication process for very large scale integrated (VLSI) devices, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use computer-aided design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance. Several different programming languages have been created for electronic design automation (EDA), including Verilog, VHDL and TDML. A typical EDA system receives one or more high level behavioral descriptions of an IC device, and translates this high level design language description into netlists of various levels of abstraction.
Physical synthesis is prominent in the automated design of integrated circuits such as high performance processors and application specific integrated circuits (ASICs). Physical synthesis is the process of concurrently optimizing placement, timing, power consumption, crosstalk effects and the like in an integrated circuit design. This comprehensive approach helps to eliminate iterations between circuit analysis and place-and-route. Physical synthesis has the ability to repower gates, insert buffers, clone gates, etc., so the area of logic in the design remains fluid. However, physical synthesis can take days to complete.
Two popular circuit simulators used in physical synthesis are SPICE and ACES. SPICE is a transistor-level simulator which depends on BSIM device models that represent model behaviors in terms complex physical equations (numerical integration formulae) embedded in code. BSIM (Berkeley short-channel IGFET model) is a physics-based, predictive metal-oxide, semiconducting field-effect transistor (MOSFET) model for circuit simulation. SPICE uses a netlist file that contains a description of the circuit with appropriate resistance, inductance and capacitance values corresponding to respective nodes as well as nonlinear devices such as transistors or diodes. An analysis is performed at an initial time, the time variable is then incremented, and an analysis is performed at that next time step, with the process repeating until the final time step is reached. ACES (adaptively controlled explicit simulation) is a transistor-level simulation technique for analysis of timing, power and noise in a variety of integrated circuits and systems. ACES depends on tabular abstractions or piecewise linear approximation to device models, and is from the family of fast simulators.
Faster performance and predictability of responses are elements of interest in circuit designs. As process technology scales to the deep-submicron (DSM) regime, it becomes more difficult to accurately model circuit performance, particularly regarding unknown behaviors of circuit components. While the foregoing simulation tools are reasonably efficient (fast) in carrying out circuit analysis, they do not adequately account for less predictable behaviors such as gate leakage in a nonlinear device (e.g., transistor). Gate dielectric leakage current becomes a serious concern, as sub-20 Å gate oxide prevails in advanced complementary metal-oxide semiconducting (CMOS) processes. Oxide layers this thin can conduct significant leakage current by various tunneling mechanisms and degrade circuit performance. The three major leakage mechanisms for a CMOS structure are electron conduction-band tunneling, electron valence-band tunneling, and hole valence-band tunneling. Each mechanism is dominant or important in different regions of operation for p-type or n-type devices. The gate tunneling current is composed of several components, including a gate-to-substrate leakage current, parasitic leakage currents through gate-to-source and gate-to-drain extension overlap regions, and gate-to-inverted channel tunneling current.
The aforementioned simulators, and in particular fast simulators like ACES, lack gate-leakage models. Gate tunneling is just one example of the difficult behaviors that need to be modeled. Most prior art simulators (whether deterministic or statistical) do not support external complex equations or complex controlled sources, and adding a new model to a simulator can be very difficult. Whenever an unmodeled device behavior arises, it takes intense effort to develop the new code for that model (e.g., BSIM) such that it is usable in a simulator like SPICE. For purposes of fast simulators, a new model means additional piecewise model variables and more engineering development effort which is also a daunting task. Offering options like complex nonlinear equations can slow down fast simulators and requires the addition of interpreters which further slow them down. These problems result in fast simulators that fail to capture secondary nonlinear and new nonlinear unmodeled behaviors.
One approach to estimating gate leakage is to replace the device in the netlist with one having an additional linear element such as a constant current source or resistor. This technique is illustrated in FIGS. 1A and 1B which depict an exemplary circuit in the form of a memory cell 4. Memory cell 4 has two cross-coupled inverters formed by transistor pairs; the left inverter has a p-type transistor PL and an n-type transistor NL, and the right inverter has a p-type transistor PR and an n-type transistor NR. The drains of the p-type transistors are connected to the power supply voltage (Vdd) and the sources of the n-type transistors are connected to electrical ground. The nodes between respective p-type and n-type transistors are storage nodes L and R with the true value of the stored data at storage node R; for example, when the stored value in memory cell 4 is zero, the voltage at node R corresponds to logical zero and the voltage at node L corresponds to logical one. Two sense transistors SL and SR couple the storage nodes to the complement bit line BLC and the true bit line BLT. The sense transistors are controlled by a word line signal WL.
FIG. 1A represents the circuit as provided in the original netlist. FIG. 1B represents a modified netlist for a memory cell 4′ wherein a resistor 6 is inserted in parallel with the gate and source of transistor NL to model gate-to-source leakage at that transistor. This approach uses a linear element for the gate leakage in the transient simulation, and does not capture the nonlinear behavior.
Another approach is to rely on two rounds of transient simulations. During the first round, the simulation is performed without the nonlinear behavior and node information is collected. An external program uses this information to build a nonlinear current waveform table. A second round of transient analysis then re-simulates the circuit using current waveforms based on first round (more than one round may be necessary). The common power analysis methodology (CPAM) power-analysis tool that uses ACES as its simulation engine relies on this approach. That tool averages out the first round node values and calculates an average gate leakage value based on this first round node info. While this approach provides some accounting for gate leakage, it is not particularly accurate.
There have been other attempts at quantifying gate leakage such as that described in the article “Efficient Techniques For Gate Leakage Estimation,” by R. Rao et al., Proceedings of the 2003 International Symposium on Low Power Electronics and Design, pp. 100-103 (2003). Those techniques use a circuit level approximation which is adequate for library characterization but not for transient analysis. The method is only applicable for gate leakage estimation once the circuit has reached steady state (i.e., the internal nodes have settled to their dc values).
In light of the foregoing it would be desirable to devise an improved method which more accurately models nonlinear behaviors in electronic devices and can easily be implemented in a fast simulator. It would be further advantageous if the method could allow transient analysis to be performed in only one round.